Western Digital this week told about plans Evolution of 3D NAND memory for years to come. Among other things, the company announced that it is developing 162-layer flash memory chips with reduced cell area and high-performance flash memory with more than 200 layers together with its Japanese partner Kioxia.
Next-generation 3D NAND memory, BiCS6, will be available later this year. At first glance, these won’t be the most advanced chips in terms of the number of vertical layers – only 162 layers, which seems quite modest against the background of the 232-layer 3D NAND chips just introduced by Micron. However, the capacity of WD and Micron solutions is the same – 128 GB (1 Tbit). An area BiCS6 and will be the most compact in the industry at 68mm2. The company was able to achieve this by significantly reducing the physical size of the memory cells, aided by the use of a new material in their structure.
In addition, the BiCS6 memory stores four bits in each cell (QLC). Reducing the physical size of the cell with a combination of writing four bits to each of them should lead to a reduction in the number of rewrite cycles, but WD has not yet announced this value. At the same time, the speed of BiCS6 storage promises 60% higher speed than modern solutions, which allows it to be used both for the manufacture of mass drives and for large server SSDs. The increase in density should also reduce production costs, which is important for everyone.
Another new development looks no less interesting – BiCS + memory with more than 200 layers. It is claimed to be designed from scratch mainly for server-side SSDs. BiCS+ storage will be available by 2024 and will offer up to 55% more bits per platter and 60% higher speed compared to BiCS6 storage. It also increases write speed by 15%, which is no less important for NAND flash memory than anything else.
Going forward, WD, like other 3D NAND vendors, is targeting 500 or more layers of 3D NAND. Such memories can only be made by a combination of many technologies, including the vertical “gluing” of memory crystals. The company isn’t giving up hope of releasing five-bit-per-cell (PLC) memory, but it’s no less difficult than releasing 500-layer 3D NAND, delaying the timing of its appearance.