The so-called second generation of the 3nm process technology carried out by TSMC usually appeared in the Taiwanese company’s internal documents under the designation N3E and was tied for implementation in the second half of 2023. At the last quarterly conference, representatives of TSMC announced that in the fourth quarter of this year the company will be ready to start mass production of chips using N3E technology.
TSMC CEO CC Wei at the reporting event At the end of that week he said verbatim: “N3E extends our family N3 through increased performance, lower power consumption and lower yield, and also offers full platform support for HPC and smartphone applications. N3E passed qualification testing, met performance and error rate targets, and will begin mass production in the fourth quarter of this year.”.
Remember that if the basic version of the N3 process technology, which TSMC has been using since late last year for the mass production of components ordered by the same Apple, offers a reduction in power consumption of up to 25-30%, a performance improvement of 10-15% and a chip area savings of up to 42% compared to the N5 process technology, this is the case in the case of N3E due to a slight reduction in transistor density (by 7.8% compared to N3). is offers a higher yield and simplifies the production itself, which has a favorable effect on the production costs. In addition, the N3E increases power savings by up to 32% compared to the N5 and increases transistor performance by 18% instead of 15% for the base N3.
In fact, the N3E sacrifices little in transistor density compared to the N5: it increases by 1.6x compared to the 1.7x of the more expensive N3 to manufacture. N3E is expected to attract more customers to TSMC’s services than N3. However, the company’s management already considers the basic version of its 3nm process technology to be the best on the market in terms of performance, transistor density and power consumption and therefore emphasizes that in the second half of the year the production of chips based on it will increase significantly both in the high-performance computing segment and in the smartphone segment.
TSMC management also expressed hope this week that the company’s 3nm process family will generate long-term demand from customers and that this technology cycle will be long-term in terms of market presence. By the end of this year, the N3 basic process technology will account for 4% to 6% of the company’s total sales, although it has not been mentioned at all in TSMC’s reports so far, although it has actually been used in mass production at least since the beginning of this year.
TSMC will not limit itself to these two variants of the 3 nm process technology. By the second half of next year, the company is preparing to master the N3P process technology, which will reduce power consumption by 5-10%, increase performance by 5% and increase transistor density by 4% compared to N3E. By 2025, N3X process technology will be introduced specifically for the most productive chips, allowing the use of higher voltages and a performance increase of at least 5%, but at the cost of higher power consumption compared to N3P. However, the density of transistors is not “touched” and remains at the same level as N3P. From this point of view, the life cycle of 3nm processes will actually be long in the TSMC manufacturing program.