The management of the largest contract manufacturer of semiconductor products at the quarterly reporting conference explained that the timing of the start of mass production of 3-nm products remains the same, but it will be possible to talk about their deliveries only at the beginning of 2023. It turns out that TSMC’s 5-nm and 3-nm technical processes in this regard will be separated by two and a half years instead of the usual two.
Even Intel, which carefully guarded the “Moore’s Law” formulated by one of the founders, has in recent years been forced to admit that its effect is slowing down, and the processor giant itself is unable to master a new technical process even once every two and a half years. Resource SemiAnalysis filtered out the statements of TSMC CEO CC Wei at the quarterly reporting conference, which was held yesterday, to highlight information related to the timing of the development of new technological processes.
Three months ago, the head of TSMC admitted that, in comparison with 5-nm technology, the terms of mastering the 3-nm technical process will be increased by at least three months. Historically, TSMC has mastered a new technical process every two years, if we talk about the moment of the start of deliveries of serial products of a new generation. Now the CEO of TSMC says that the company will begin to receive revenue from the supply of 3nm products only in the first quarter of 2023, although the actual production will be launched in the second half of 2022. This difference is due to the increased lead time. In fact, between the start of deliveries of the first 5-nm and 3-nm products, respectively, two and a half years will have passed, and not two, as before.
It is obvious that TSMC in the early stages will be limited in the performance of the equipment used to process 3nm products. Ultra-hard ultraviolet (EUV) lithography within the 3nm process will be used more actively, and the number of available scanners is still limited. Component shortages and logistics difficulties have also affected ASML’s ability to supply its main customer, TSMC, with sufficient lithography equipment.
Indirectly, such fears are confirmed by the comments of the head of TSMC, who explained that about a year after the development of the basic version of the 3-nm technical process (N3), the company will offer its customers an improved version of N3E, improvements will be aimed not only at increasing the speed of transistors, but also reducing the defect rate and shorter production cycle times. At cost, both versions of the 3nm process will be the same. According to unofficial data, one 300 mm silicon wafer with 3-nm chips will cost customers $ 20,000 apiece, although a similar wafer with 5-nm crystals costs about $ 16,500.
The news, determined by the speech of the TSMC management, allows the representatives of the SemiAnalysis website to conclude that Apple smartphones of the 2022 sample will not be equipped with 3-nm processors. Moreover, the head of TSMC at the last conference told about the refusal of a certain client from his intentions to order 3-nm products for an earlier period compared to the second half of next year. By the way, the risky production of 3-nm TSMC products is only going to start in the time remaining until the end of this year. But TSMC management does not doubt the competitiveness of its 2-nm technical process, mentioning 2025 in the context of its implementation. At least in terms of density of transistors and their speed, the company expects to remain the leader.
It turns out that when mastering 2-nm technology, TSMC will withstand an interval of two and a half years relative to the previous stage of lithography. Intel and Samsung are also ready to offer their technological processes similar in parameters by 2025, if not earlier, so TSMC will have to make some efforts to maintain technological leadership.