For a year and a half, Intel has been proclaiming literally on every corner that it wants to regain its technology leadership in the field of lithography by 2025. By that time, it will master the Intel 18A process, and a year earlier, as part of the 20A technology, will begin to use transistors with the RibbonFET structure and PowerVIA circuitry with power supply from the back of the chip. Based on new comments from TSMC officials, the Taiwanese Intel competitor will not offer its customers the latest innovations until 2026 at the earliest.
At the latest quarterly reporting conference, TSMC CEO CC Wei said explainedthat the company masters the N2 process according to plan and will move into mass production in 2025. TSMC will use a new structure of transistors with so-called nanosheets (with a circular gate) as part of the N2 technology – Intel, on the other hand, expects to introduce its variant called RibbonFET as early as 2024, given a good combination of circumstances. According to TSMC’s CEO, nanosheet technology will provide the company’s customers with the best combination of performance and power consumption on the market within the N2 standards, as well as the highest transistor density. This will enable TSMC to expand its technology leadership until the N2 process technology comes to market, the company said.
However, it should be noted that Intel will implement its RibbonFET structure as part of the 20A process technology next year – at least at the prototype level. From this point of view, given the mention of TSMC representatives about the launch of nanosheets in 2025, the American chipmaker can claim a leadership role in launching such an innovation.
The CEO of TSMC casually reminded that the company will introduce circuitry from the back of the chip as part of the N2 family of process technologies. According to him, this innovation will be more in demand in the high-performance computing segment. Compared to the basic version of N2, the switching speed of the transistors increases by 10-12% and the density of the transistors increases by 10-15%. Technically, TSMC will offer this chip power scheme in the second half of 2025, but it will not be available to consumers in mass production until 2026. This means that TSMC will also lag behind Intel here, all at once by a year and a half to two years, barring the latter’s unforeseen delays.
The TSMC boss added that the company sees high customer interest in the technical processes of the N2 family, both from developers of high-performance chips and in the smartphone segment. Speaking to analysts at a reporting event, TSMC officials had to admit that by changing its technical processes, the company is able to gradually increase the speed of transistors. In the framework of N2 technical processes, it will also not be possible to achieve a noticeable increase in performance compared to previous standards, however, as customers have recently increasingly focused on improving energy efficiency, the company has decided to pay due attention to this optimization when mastering this lithography technology. According to the TSMC boss, this is highly appreciated in the data center segment.