At the ISSCC 2023 conference, representatives from SK hynix gave a presentation in which reported about the development of the world’s first 3D NAND memory with over 300 layers. The document was prepared by 35 engineers of the company, which once again underlines the complexity of improving the technical process of manufacturing multilayer flash memory. It is remarkable that the developers have not only significantly increased the recording density, but also the bandwidth of the chips: from 164 MB/s to 194 MB/s.
It’s easy to understand that SK hynix engineers have been working on two key and important areas: increasing recording density (reducing the cost of storing each bit of data) and increasing performance. With the advent of “multi-level” 3D NAND, increasing recording density has become fairly simple in principle, but difficult to implement—this means increasing the number of layers while decreasing the pitch between layers. Both lead to an increase in the resistance of the word line (WL) line connecting the cells in the array row. This growth must be compensated for in one way or another, otherwise speed and power efficiency will suffer.
A prototype NAND memory chip presented by SK hynix with more than 300 layers consisted of three-bit cells (TLC) and had a capacity of 1 Tbit. By increasing the number of layers, the cell density increased from 11.55 Gbit/mm2 with current 238-layer memory up to more than 20 Gb/mm2. The overall storage performance has been increased in five different ways, generally aimed at speeding up the writing, erasing and reading processes. To do this, we had to make changes to the sequences and timings of commands.
In particular, the Triple Program Verification Procedure (TPGM) was implemented instead of the previous double DPGM verification. The new version divides the cells into four instead of three groups. The TPGM technology reduces the tPROG parameter and this together with the increased split reduces the cell programming time by about 10%.
In addition, the tPROG parameter is reduced by the new Adaptive Uns selected Line Precharge (AUSP) technology. This speeds up work with cells by about 2%. Slightly more speed is achieved by reducing the capacitive loading on the WL line, resulting in the programmable dummy string (PDS) method. The All Pass Rise (APR) technique results in a reduction in read time (tR), which translates into a decrease in the response time of the WL line to a new voltage level, improving read time by 2%. Finally, Plane Level Reread (PLRR) is used to improve quality of service during erasure.
All of this together, as mentioned above, made it possible to increase the speed of the 1 Tbit 3D NAND TLC from Hynix and SK over the generation from 164 MB/s to 194 MB/s while increasing the recording density at the same time. To be clear, company officials have not disclosed the production schedule for the release of the NAND 300+ memory, and hardly could. It is expected that it will not be released until early next year at the earliest. In the meantime and in the current year, memories with over 230 layers will enter production, the release of which has been established to some extent by all major players in the NAND memory market.