Kioxia and WD unveil 218 layer 3D NAND claiming its the
Hardware

Kioxia and WD unveil 218-layer 3D NAND, claiming it’s the world’s densest flash memory

Kioxia and Western Digital announced 3D NAND flash memory chips with 218 layers with a capacity of 1 Tbit. Chips are manufactured on both three-bit cells (TLC) and four-bit cells (QLC). According to the developers, the chips have the highest bit density in the industry. Samples of new products have already been received by a limited number of the companies’ customers for evaluation. The new memory will find its way into smartphones, internet devices and SSDs.

    Image source: Kioxia

Image source: Kioxia

The new memory belongs to the eighth generation of BiCS FLASH from Kioxia and Western Digital. The ninth generation will open chips with more than 300 layers. Partners use crystal “gluing” to increase the number of layers. In addition, with new products, as can be seen from the context of the press release, the cell array and controller are manufactured separately and also joined together in a “gluing” process to form a vertical stack.

Previously, Kioxia and Western Digital made controllers as part of cell arrays. The first to separately produce a control chip was the Chinese company YMTC in the form of Xtacking technology. In the case of the 218-layer BiCS FLASH memory from Kioxia and Western Digital, we are talking about the “innovative technology” CBA (CMOS direct Bonded to Array), in which controllers and cell arrays are manufactured on separate wafers with optimization of each process. and are combined only after full processing (or crystals of controllers and arrays are combined after cutting). This point is not clarified in the official document.

The array of cells is still used “four-level” – from four separate array levels, which allows you to speed up memory due to parallelism. The arrays were also “shrunk” vertically and horizontally in the production of 218-layer assemblies. This (more precisely, the lateral shrinkage of the cells) made it possible to increase the bit density by 50%. In addition, memory performance has been increased by 60% compared to the previous chip generation. This means that the speed of work on each contact of the data bus has increased to 3.2 Gb / s.

Write speed is also faster, by about 20%. Read latencies have also been reduced, which will also have a positive effect on the performance of the new 3D NAND chips from Kioxia and Western Digital. In general, this memory will be a new springboard for more productive devices and applications, which can be expected by the end of this year.

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Dylan Harris

Dylan Harris is fascinated by tests and reviews of computer hardware.

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