Intel presented second generation neuromorphic chips: Loihi II. Conceptually and architecturally, the new chip, as a whole, repeats the first generation, announced four years ago, but has a number of technical and software improvements. But more interestingly, with the release of Loihi II, which is still considered a research development, the company is ready to take the first steps towards a limited commercialization of this solution.
Within the framework of the neuromophoric approach, researchers are trying to recreate in hardware, with varying degrees of accuracy, the mechanisms underlying the brain, which at first glance are quite simple: signals propagate asynchronously and in parallel along a densely knitted and time-changing network of neurons as a response to external events.
Attempts to repeat this within the framework of conventional “hardware” can be considered quite successful, because now you will not surprise anyone with neural networks. However, such networks require expensive preliminary training on pre-labeled data, while the brain learns on the fly. And with the growth of the complexity of the models, the issue of energy efficiency arises, and not only training, but also execution.
Cerebras WSE-2 can be considered the “pinnacle of evolution” of classical AI accelerators today: a chip the size of a silicon wafer contains 850 thousand cores and consumes 15 kW. But this is not enough – according to the developers themselves, only cluster of such chips is capable of working with AI models comparable in scale to the human brain. And all these limitations are intended to eliminate precisely neuromorphic systems.
Loihi II is manufactured using Intel’s EUV 4 process technology, which is still under development. The chip has an area of 31 mm2 and contains 2.3 billion transistors, and the area of one core is 0.21 mm2, that is, the density in comparison with the first generation has almost doubled. The chip still contains 128 neural cores, but the number of available neurons has grown from 128 thousand to 1 million.The amount of memory per core has slightly decreased, from 208 to 192 KB, but now memory banks can be more flexibly distributed between neurons and synapses, and compression allows you to use the available volume even more efficiently.
The cores themselves have changed too. In the first generation, they were optimized for specific impulse neural networks, and now each core has its own programmable pipeline, and the models themselves at the chip level are set by microcode. In addition, up to 4096 bytes can be used for the state of the neuron, depending on the tasks (previously there were only 24 bytes). The number of synapses per chip has decreased from 128 to 12 million, but they received a significant upgrade – an INT32 value is used to encode the signal, and not a binary (yes / no).
Together, this allows you to use learning (including on the fly) with third factor… However, the instruction set of neuromorphic nuclei is still simple. It includes basic arithmetic operations, shifts, branching, memory / register and pulse handling. The cores themselves are connected by a fast 8 × 16 mesh network, and six more dedicated cores (previously there were only three) with hardware acceleration of the corresponding tasks are responsible for the network configuration, (de-) data encoding and pulse transmission control.
The total effect of all the innovations is such that the Loihi II is faster than the first generation Loihi by about an order of magnitude. Moreover, it received improved scalability: up to 1000 cores on the chip itself, and you can also form a three-dimensional mesh network of chips thanks to six dedicated I / O controllers on each of them and four times faster lines. And for communication with the outside world, standard SPI / AER, GPIO and 1 / 2.5 / 10GbE interfaces are now available.
The first device based on Loihi II was the Oheo Gulch single-chip card for software development and debugging. It is currently only available to select Intel partners in the Neuromorphic Research Cloud. The next device will be the compact (4 “× 4”) Kapoho Point board, which already carries eight Loihi II chips and provides Ethernet and GPIO, as well as various interfaces for sensors and actuators. The boards can be directly connected to each other for easy expansion of computing power. In the future, it is possible to integrate chips into hybrid SoCs for various tasks, as well as the emergence of solutions for data centers.
In general, the areas of application and tasks of the new products coincide with those that are now served by “classical” neural networks (adjusted for energy efficiency). However, one “hardware” for distribution is not enough, so Intel has prepared a universal open source framework LAVA, which will unify the development and preparation of models for almost any hardware solutions (not only neuromorphic), taking into account the specifics of specific architectures.