At the Hot Chips 2023 conference, Intel talked about how it will rethink its server processors in the near future. Construction details have been announced for Granite Rapids and Sierra Forest and will be released next year. These processors are becoming modular, easily scalable, and adopting a chiplet layout (tiled in Intel terminology). You will use up to three arithmetic chiplets and up to two input-output chiplets.
As per the Intel report, the chiplet structure of processors will be introduced not only in the consumer Meteor Lake, but also in the Granite Rapids and Sierra Forest servers, which will be released in 2024 as part of the Birch Stream platform. The computing chips for both processors will be made using Intel 3 technology, the next closest to Intel 4 used in the manufacture of Meteor Lake and the first in which the company plans to use EUV lithography. The chiplets that make up Granite Rapids and Sierra Forest will be connected via EMIB bridges.
Although both types of processors are based on the same platform, the difference between them is conceptual. Granite Rapids will be based on high-performance cores, while Sierra Forest will be processors made entirely of energy-efficient cores. This determines the composition of their chiplets. Therefore, unlike consumer CPUs, Intel will not use a hybrid design in server solutions.
The Redwood Cove architecture, which will make its debut in Meteor Lake, will be used in the productive P-cores of future server CPUs. The Redwood Cove cores will get an L1 cache increased to 64 KB for instructions, branch prediction optimizations, improved algorithms for working with the memory, etc. Chiplets based on Redwood Cove are said to have up to 40 cores and up to 160 MB of L3 cache, which would theoretically allow building a 120-core Granite Rapid with nearly half a gigabyte of cache.
Energy-efficient E-Cores will also move to the Crestmont architecture shared with Meteor Lake, which, like Redwood Cove, will find its place in some optimizations. At the same time, such cores retain a cluster layout with a single 4MB L2 cache for four cores. Thanks to a special “compacted” design, Intel wants to pack up to 72 E cores in one chiplet, which theoretically means the possibility of a Sierra Forest with 144 cores. There is also a reverse possibility: in a Crestmont cluster, two cores can be disabled, allowing the creation of Sierra Forest variants with increased cache memory. AVX-512 support isn’t expected to appear in Crestmont, but Intel says Sierra Forest processors won’t exceed a TDP of 205 watts, even if they have over a hundred cores.
Unlike AMD, which places the memory controller on the I/O chiplet, Intel will leave the memory controller on the same chiplet as the computing cores. Each chiplet will support eight DDR5 channels, but generally server processors don’t run more than 12 memory channels, even when composed of three computing chiplets. At the same time, the integrated memory controller will be fundamentally revised and will receive support not only for the usual DIMMs, but also for new MCR modules (with rank multiplexing), which use parallel ranks at the architecture level. According to Intel, this technology will increase throughput by 30-40%.
The I/O chiplets will house a universal UPI/PCIe 5.0/CXL 2.0 controller, external interfaces and additional coprocessors if required. Such chiplets are made using Intel 7 technology and can coexist in a server processor. In total, Xeon can implement up to 136 PCIe 5.0/CXL 2.0 lanes and up to 6 UPI interprocessor connections.
Under the current version of the plans, Sierra Forest processors will be the first to market, however, Granite Rapids is expected to come to market “shortly thereafter”. In a recent quarterly report, Intel indicated that the Intel Process 3 process is on track and will enter volume production in the first half of 2024. That means the first Sierra Forest could be announced in less than a year.