The next IEEE Solid State Circuit conference will take place in San Francisco from February 18 to 22, where leading chip developers will talk about promising projects. Specifically Intel, Marvell and Synopsys Will inform about our own developments in the area of signal interfaces for RAM of the future. Each of them presents circuits for 3nm process technology with speeds up to 224 Gbit/s.
The DDR6 memory standard specifications are expected to be adopted in 2024. The data transfer rate on each data bus pin is between 12.8 Gbit/s and 17 Gbit/s. Of course, this requires updated protocols and new circuit solutions. Intel, Marvell and Synopsys are each preparing in their own way for the introduction of DDR6 and future RAM versions, which they plan to talk about in more detail in February.
Intel’s report goes into the organization of the physical layer (PHY) of the memory signal interface, which, as you can imagine, is essentially analog. At this stage, it is important to reduce the noise level and ensure the best synchronization of signals, which in turn depends on the characteristics of the transistors and directly on the manufacturing process of the controller. Intel has reportedly adapted the DAC circuit for 3nm FinFET transistors. The consumption is 3 pJ/bit, which is very good since the increase in consumption should remain limited even with an increase in throughput.
Synopsys, in turn, presents licensed (IP) circuits for a transceiver with similar properties. The Synopsys solution also offers a maximum interface speed of up to 224 Gbit/s with consumption of up to 3 pJ/bit. Synopsys circuits are also designed for 3nm FinFET process technology. Incidentally, this ignores Samsung, which is switching to circular gate transistors (GAAFET) as part of 3 nm production.
Finally, Marvell, a well-known developer of controllers and signal processors, including solutions for SSDs, presents its solution for high-performance RAM of the future. The Marvell digital controller in the form of a signal processing and transmission unit will enable operating speeds of up to 212 Gbit/s for the 5nm FinFET process technology. The significant headroom in operating speed leaves room for further increases in RAM speed beyond expectations for the DDR6 standard, which is important for AI and machine learning applications.