reportedKioxia and WD will present a paper on today’s most advanced 300+ layer 3D NAND memory at the upcoming 2023 VLSI Symposium in June. Technologies will also be presented that will increase the speed of flash memories, for which a number of measures have been taken, including increasing the number of levels in each layer – separately working arrays of cells.
It is easy to see that the partners will go down the path of increasing parallelism when working with 3D NAND. More individual cell arrays on a chip (planes or plans) – more data can be processed at the same time. Today there are traditionally two or four such aircraft on one chip, but Kioxia and WD have increased the number of aircraft to eight.
But that’s not all! The new memory with 210 active layers (although the same technique can be implemented in the recently announced 218-layer 1-Tbit 3D TLC-NAND) involves reading two adjacent memory cells with a clock pulse (strobe). The partners call this approach “one-pulse-two-strobe,” and it also increases the bandwidth of the new storage. In its purest form, this reduces total memory read time by 18%.
Another innovation was the introduction of a hybrid line address decoder (X-DEC). The new memory, with eight separate cell arrays in each layer, heavily densified wiring, which could degrade read latency. Data transfer between storage and host has also been accelerated by reducing the data request area in the X-direction by up to 41%. The decoder mitigates all of these effects of the chip’s architecture and design complexity, reducing latency to 40ms, which is even better than both companies’ 128-layer serial 3D NAND chips (they have that number for 56ms) .
As a result, the parallelism and improved architecture increase the throughput of the 210-layer memory to 205 MB/s. That’s right, of course you need to create quite complex controllers for this. There is a risk that the controller will not be able to handle the load balancing across eight tiers in each tier and 210 tiers above, resulting in a reduction in performance rather than an increase. We add that the operating speed for each contact of the data bus is 3.2 Gbps – like the new 3D NAND with 218 layers. All these findings can therefore already be implemented in mass-produced microcircuits.
In addition to developing eight-level structures, the partners will present a solution to create 3D NAND with more than 300 layers. For this it is necessary to increase the length of the vertical through channels and improve their quality – it should be good with a margin for “higher” microcircuits. To achieve these goals, the companies want to use the so-called metal-enhanced lateral recrystallization (MILC) process.
Nickel silicide is used to remove impurities and eliminate defects in the channel. The companies have developed an experimental 112-layer chip with 14-micron holes based on this technology. Measurements have shown that read noise is reduced by at least 40% and channel conductivity increased by a factor of 10 without compromising cell reliability. By the way, memory with more than 300 layers was also presented in the form of a project or even a prototype of SK Hunix, and we can also hear about it at the upcoming symposium.
Finally, a report from Tokyo Electron is expected. This etch tool maker is in the process of presenting a method to quickly etch 10+ micron (10 µm) vertical channels for 400-layer 3D NAND without excessive power consumption or the use of toxic substances. The high aspect ratio (HAR) dielectric etch technology is said to use a cryogenic wafer step and new gas chemistry to create 10-micron high channels with a “superior” etch profile in just 33 minutes and with an 84% reduced carbon footprint. We await details.